In recent years, LDPC code is becoming a focus of attention as error correcting code that yields high error correcting performance. LDPC code is error correction code defined by a low-density parity check matrix.
Since the LDPC code has high error correcting performance and can be easily mounted, the LDPC code is being considered as an error correcting coding scheme for an IEEE802.11n high speed wireless LAN (Local Area Network) system, digital broadcasting system or large-capacity storage apparatus or the like.
One example of a conventional LDPC code decoding apparatus is disclosed in Patent Literature 1. The decoding apparatus described in Patent Literature 1 is a decoding apparatus adaptable to a plurality of check matrices and classifies check matrices so that edges are included in a unit region. Here, the “edge” refers to element “1” of a check matrix. In the case of LDPC code in binary notation, elements of a check matrix are “0” or “1.” The “elements of a matrix” represent components of the matrix. The decoding apparatus described in Patent Literature 1 stores edge arrangement information of edges located in a classified group and thereby reduces the memory capacity. Furthermore, Patent Literature 1 describes a method of simplifying connections between memory and calculation processors using the edge arrangement information.